Freescale i.MX IPUv3
====================

Required properties:
- compatible: Should be "fsl,<chip>-ipu"
- reg: should be register base and length as documented in the
  datasheet
- interrupts: Should contain sync interrupt and error interrupt,
  in this order.

example:

ipu: ipu@18000000 {
	compatible = "fsl,imx53-ipu";
	reg = <0x18000000 0x080000000>;
	interrupts = <11 10>;
};

Freescale i.MX LCDC controller
==============================

Required properties:
- compatible: Should be "fsl,<chip>-lcdc"
- reg: should be register base and length as documented in the
  datasheet
- interrupts: Should contain interrupt

example:

lcdc: lcdc@10021000 {
	compatible = "fsl,imx27-lcdc", "fsl,imx21-lcdc";
	reg = <0x10021000 0x4000>;
	interrupts = <61>;
};

Parallel display support
========================

Required properties:
- compatible: Should be "fsl,imx-parallel-display"
- crtcs: the crtc this display is connected to, see below

Optional properties:
- interface_pix_map: Defines a pixel mapping onto the 24-bit IPU
  Display Interface bus to the display. Internally the IPU represents
  pixels in either RGB24 or YUV444 format. This property tells the IPU how
  to map those RGB24 or YUV444 pixels onto the display interface bus.
  The data format is as follows:

  interface_pix_map = <c0-dest-msb c0-src-mask c1-dest-msb c1-src-mask
  		       c2-dest-msb c2-src-mask>;

  where:
	c0, c1, c2: are the color components (c0 = B/V, c1 = G/U, c2 = R/Y)
	src-mask: is the mask of component source bits to be forwarded
	          to the DI bus
	dest-msb: defines where to place those component bits on the
	          24-bit DI bus, represented as the MSBit on the bus.

- interface_pix_fmt: A name given to the pixel format sent to the display.
  The following are names with pre-defined pixel mappings that do not
  require an explicit interface_pix_map property: "rgb24", "rgb565", "rgb666"

- edid: verbatim EDID data block describing attached display.
- ddc: phandle describing the i2c bus handling the display data
  channel

example:

display@di0 {
	compatible = "fsl,imx-parallel-display";
	edid = [edid-data];
	crtcs = <&crtc0>;
	interface_pix_fmt = "rgb24";
};

Pixel map examples:

This example defines a new format named "bgr565" using a pixel map:

display@di0 {
	compatible = "fsl,imx-parallel-display";
	edid = [edid-data];
	crtcs = <&crtc0>;
	interface_pix_fmt = "bgr565";
	interface_pix_map = <15 0xf8 10 0xfc 4 0xf8>;
};

This example defines an unnamed format where an rgb666 format is shifted
up by 6 bits on the DI bus:

display@di0 {
	compatible = "fsl,imx-parallel-display";
	edid = [edid-data];
	crtcs = <&crtc0>;
	interface_pix_map = <11 0xfc 17 0xfc 23 0xfc>;
};


LVDS display bridge (LDB)
=========================

Required properties:
- compatible: Should be "fsl,<chip>-ldb"

For each of the enabled channels lvds node should contain a child node:
Required properties:
- compatible: Should be "fsl,<chip>-ldb-channel", "fsl,imx-ldb-channel"
- fsl,ldb-channel: channel index (0 or 1)
- crtcs: the crtcs the ldb channel is allowed to connected to, see below

Optional properties:
- edid: verbatim EDID data blocks describing the displays attached to channel.
- ddc: phandle describing the i2c bus handling the display data channels
  for the channel.

lvds@53fa8008 {
	compatible = "fsl,imx6q-ldb";
	ldb-ch@0 {
		compatible = "fsl,imx6q-ldb-channel", "fsl,imx-ldb-channel";
		fsl,ldb-channel = <0x0>;
		crtcs = <&crtc0 &crtc2>;
		edid = [edid-data];
	};

	ldb-ch@1 {
		compatible = "fsl,imx6q-ldb-channel", "fsl,imx-ldb-channel";
		fsl,ldb-channel = <0x1>;
		crtcs = <&crtc1 &crtc3>;
		ddc = <&i2c0>;
	};
};

Specifying CRTCs connected to display output devices
====================================================

Display output device nodes should specify which CRTCs they can be
connected to in their crtcs property, containing a 'crtc-list':

	crtc-list ::= <crtc-phandle ...>
	crtc-phandle : phandle to device node providing the crtc

In the following example, two image processing units ipu0 and ipu1
provide two CRTCs each. The hdmi connector can be connected to either
CRTC of ipu1 (crtc2 and crtc3), and the lvds connector is fixed to the
second CRTC of ipu0 (crtc1). And the parallel display is fixed to
the LCD CRTC.

	hdmi: hdmi {
		ddc = <&i2c2>;
		crtcs = <&crtc2 &crtc3>;
	};
	lvds: lvds {
		edid = [edid-data];
		crtcs = <&crtc1>;
	};
	parallel-display {
		crtcs = <&lcdc>
	};

